UNIVAC 1103

From Academic Kids

The UNIVAC 1103 or ERA 1103, a successor to the UNIVAC 1101, was a computer system designed by Engineering Research Associates and built by the Remington Rand corporation in October, 1953.

The UNIVAC 1103 had 1024 words of 36 bit Williams tube memory (first commercial computer to use random access memory). Each of the 36 Williams tubes was 5-inchs in diameter. A magnetic drum memory provided 16,384 words. Both the electrostatic and drum memories were directly addressable: addresses 0 through 01777 (Octal) were in electrostatic memory and 040000 through 077777 (Octal) were on the drum.

Fixed-point numbers had a 1 bit sign and a 35 bit value, with negative values represented in one's complement format.

Instructions had a 6 bit operation code and two 15-bit operand addresses.

Programming systems for the machine included the RAWOOP one-pass assembler and SNAP floating point interpretive system authored by the Ramo-Wooldridge Corporation in Los Angeles, the FLIP floating point interpretive system by Consolidated Vultee Aircraft in San Diego, and the CHIP floating point interpretive system by Wright Field in Ohio.

History

Even before the completion of the Atlas (UNIVAC 1101), the Navy asked Engineering Research Associates to design a more powerful machine. This project became Task 29, and the computer was designated Atlas II.

In 1952, Engineering Research Associates asked the Armed Forces Security Agency (the predecessor of the NSA) for approval to sell the Atlas II commercially. Permission was given, on the condition that several specialized instructions would be removed. The commercial version then became the UNIVAC 1103. Because of security clearances, Remington Rand management was unaware of this machine before this.

Remington Rand announced the UNIVAC 1103 in February 1953. The successor machine was the UNIVAC 1103A or Univac Scientific, which improved upon the design by replacing the unreliable Williams tube memory with magnetic core storage, adding hardware floating point instructions, and a hardware interrupt feature.

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